Semiconductor circuits are currently manufactured in planar technology. The complexity that can be achieved on a chip is limited by the size thereof and by the structural fineness that can be achieved. In conventional technology, the performance of a system composed of a plurality of semiconductor chips connected to one another is significantly limited by the limited number of possible connections between individual chips via terminal contacts, by the low speed of the signal transmission via such connections between various chips, the limited speed in complex chips due to highly branched interconnects and the high power consumption of the interface circuits.
These indicated limitations given the employment of planar technology can be overcome with three-dimensional techniques of the circuitry. The arrangement of a plurality of components above one another allows a parallel communication of these components with little outlay for electrically conductive connections in a level. Moreover, speed-limiting interchip connections are avoided.
A known method for the manufacture of three-dimensional ICs is based on depositing a further semiconductor layer over a level of components and recrystallizing this further semiconductor layer via a suitable method (for example, local heating by laser) and realizing a further component level therein. This technique also exhibits significant limitations that are established by the thermal load on the lower level in the recrystallization and the obtainable yield limited by defects.
In an alternative method, the individual component levels are manufactured separately from one another. These levels are thinned to a few .mu.m and connected to one another by wafer bonding. The electrical connections are produced in such a way that the individual component levels have their front side and back side provided with contacts for the interchip connection.
U.S. Pat. No. 4,939,568 discloses a vertically integrated semiconductor component and an appertaining manufacturing method, whereby the vertical, conductive connection ensues via vertical metal pins that are located in the substrate of a respective layer level. The manufacturing method provides that the back side of the substrate, which is not provided with a layer structure, be ground down until these vertical conductive connections are uncovered. This side of the substrate can then also be provided with structures. For a direct connection to a following level of the component, the uncovered surfaces of the vertical conductive connections are provided with aluminum contacts.
DE 43 14 907 C1 discloses a manufacturing method for vertically integrated components wherein the component levels are first generated on separate substrates. The two substrates are connected to one another after the application of a planarization layer on the lower substrate and the thinning of the upper substrate. Integrated, pin-shaped metal structures are provided in the substrate for the electrically conductive connection between component levels.
DE 44 00 985 C1 discloses that polyimide be employed for the planarization level, that via holes be generated first for the connection of the component levels and that these be subsequently filled with a contact material. The polyimide layer is disadvantageous in this embodiment, this layer splitting water off during hardening (or, respectively, imidization) and exhibiting a reaction contraction. Water that is split off remains largely in the component and leads to additional stresses that can degrade the finished component in terms of its function or durability. Further, a polyimide layer has only a slight planarization effect of, for example, 30%, so that a plurality of layers are required that in turn exhibit adhesion problems relative to one another.